1. Field of the Invention
The present invention relates to a master slice integrated circuit having a memory region formed by macrocells, and more particularly, it relates to technique for improving a degree of integration in a master slice integrated circuit.
2. Description of the Prior Art
In a master slice large-scale integrated circuit (LSI), a logic circuit and a memory are often formed on a single gate array chip. In order to maintain universality of the gate array chip, the memory is preferably formed by an array of macrocells, not by a memory-dedicated region (a region dedicated only to a memory). FIG. 1 illustrates a first example of a gate array chip, which can be provided thereon with a memory and a logic circuit formed by macrocells.
Referring to FIG. 1, a gate array chip 16a is formed thereon with a parallel array of strip-shaped active areas 18. Strip-shaped wiring areas 19 of width D1 are arranged between respective adjacent pairs of the active areas 18. A plurality of input/output interface buffer areas 17 are formed to enclose the parallel array of the active areas 18.
FIG. 2 is a partially enlarged view of FIG. 1. Each of the active areas 18 is formed by a one-dimensional array of basic transistor cells 20. Macrocells for the logic circuit and the memory can be formed by interconnecting such basic transistor cells 20. As shown in FIG. 3, ten to forty lateral wires 21, for example, can be formed in each wiring area 19. Namely, the width D1 of each wiring area 19 is so determined as to receive ten or more lateral wires 21.
The parallel array of the active areas 18 as shown in FIG. 1 is partially employed as a memory region MR, and the remaining part is employed for the logic circuit. Since a large number of the lateral wires 21 are required for forming the logic circuit, the width D1 of the wiring areas 19 is preferably large to some extent, in order to form the logic circuit. On the other hand, the memory region MR requires no large number of lateral wires, but the most part of wires are formed by vertical wires 22 such as word lines. The width D1 of the wiring areas 19 is preferably small in order to form the vertical wires 22. If the width D1 is large, the vertical wires 22 are followingly increased in length, to reduce the degree of integration and the operating speed of the memory region MR.
Thus, the width D1 required for the logic circuit is contradictory to that required for the memory region MR. If the requirement for the logic circuit is satisfied, the degree of integration and the operating speed MR are undesirably reduced. In the conventional device, the width D1 is set within a range of 40 to 80 .mu.m.
FIG. 4 shows another conventional gate array chip 16b, which has been developed in order to improve the degree of integration of a master slice LSI. Continuously arrayed stripshaped active areas 18 are provided on the gate array chip 16b. Wiring areas 19 are provided only around the array of the active areas 18, but not between adjacent ones of the active areas 18. Such situation can also be understood from FIG. 5, which is a partially enlarged view of FIG. 4. If lateral wires are required between any adjacent pair of active areas 18, one or more active areas 18 are employed as wiring areas. As shown in FIG. 6, for example, an active area 18b provided between active areas 18a and 18c is employed as a wiring area 19a, which is provided thereon with lateral wires 21. The maximum number of such lateral wires 21, which can be provided in the wiring area 19a, is defined by width (vertical width in FIG. 6) of the active area 18b. Therefore, a plurality of continuous active areas are employed as wiring areas if a large number of lateral wires 21 are required.
In a master slice LSI formed by such a gate array chip 16b, the wiring areas to be provided between adjacent pairs of active areas used for macrocells can be changed in size at need. However, the size of such wiring areas must be integral times the width of the active areas 18. For example, when each of the active areas 18 can receive nine lateral wires 21 while required are thirteen lateral wires 21, two active areas 18 are employed as wiring areas. In this case, a space for (9.times.2-13)=five wires is not used and wasted. Thus, the degree of integration is not increased also in the gate array chip 16b as shown in FIG. 4.
The degree of integration is further reduced by positional relation between a logic circuit region and a memory region on the gate array chip 16b. If a logic circuit region LR and a memory region MR are adjacent to each other longitudinally along active areas 18 as shown in FIG. 7, vertical width of wiring areas 19a is determined by the number of lateral wires 21 required for the logic circuit region LR. In other words, the number of the lateral wires 21 required for interconnecting logic macrocells 23, which are shown with slanting lines, defines the size of the wiring areas 19a. Thus, the vertical interval of memory macrocells 4 formed by the active areas 18 is undesirably increased, to increase the length of vertical wires 22 such as word lines. Since the vertical width of the wiring areas 19a is restricted to integral times the vertical width of the active areas 18, the wiring areas 19a occupy spaces in excess of those substantially required for the respective ones of the logic circuit region LR and the memory region MR.
Increase in length of the vertical wires 22 applies unwanted load on the operation of the entire circuit formed on the gate array chip, whereby the operating speed of the circuit is reduced.